(1) Field of the Invention
This invention relates to a semiconductor device and a method for fabricating such a semiconductor device and, more particularly, to a semiconductor device in which plural kinds of transistors are formed on one substrate and a method for fabricating such a semiconductor device.
(2) Description of the Related Art
To increase the operating speeds of high-breakdown-voltage transistors used in organic electroluminescence (EL) panels, liquid crystal display (LCD) drivers, ink jet printers, and the like, in recent years there have been intense demands for the formation of such high-breakdown-voltage transistors and logic transistors to be fabricated especially on the basis of the process rule of 0.35 μm or less on one substrate.
At present, a salicide process is usually adopted for forming 0.35-micrometer-or-less logic transistors in order to form shallow junctions in their source and drain regions or reduce contact resistance. If logic transistors formed with high-breakdown-voltage transistors on one substrate must operate at high speeds, such salicide is indispensably formed. In a salicide process usually adopted, salicide is also formed on at least contact regions, such as a source region and a drain region, in each of the high-breakdown-voltage transistors formed with the logic transistors on the one substrate. With salicide formed in a high-breakdown-voltage transistor, contact resistance can be reduced, but breakdown voltage may drop depending on, for example, where the salicide is formed.
A semiconductor device for securing a sufficiently high breakdown voltage even in the case of salicide being formed has conventionally been proposed (see Japanese Patent Laid-Open Publication No. 2004-111746). In Japanese Patent Laid-Open Publication No. 2004-111746, if high-breakdown-voltage transistors and logic transistors, for example, are formed on one substrate, a high impurity concentration region is formed in a low impurity concentration region but its periphery in a drain region between a gate electrode and an isolation region of each high-breakdown-voltage transistor where a high voltage is applied at a distance from the isolation region. Salicide is then formed on the high impurity concentration region but its periphery. By forming the salicide, contact resistance can be reduced. In addition, by forming the high impurity concentration region inside the low impurity concentration region, electric field concentration which occurs at the time of voltage being applied to a drain is lessened and a sufficiently high breakdown voltage is secured.
By the way, if a semiconductor device in which logic transistors and high-breakdown-voltage transistors are formed on one substrate is fabricated, the following problems may arise when a sidewall is formed on the sides of a gate electrode of each logic transistor.
FIG. 32 is a schematic sectional view showing an important part of an example of a sidewall formation process.
As shown in FIG. 32, the case where an n-channel logic transistor, a p-channel logic transistor, an n-channel high-breakdown-voltage transistor, and a p-channel high-breakdown-voltage transistor are formed on a silicon (Si) substrate 200 is taken as an example. A logic transistor section 210 where an n-channel logic transistor is formed, a logic transistor section 220 where a p-channel logic transistor is formed, a high-breakdown-voltage transistor section 230 where an n-channel high-breakdown-voltage transistor is formed, and a high-breakdown-voltage transistor section 240 where a p-channel high-breakdown-voltage transistor is formed are defined by isolation regions 201a and 201b, the isolation region 201b and an isolation region 201c, the isolation region 201c and an isolation region 201d, and the isolation region 201d and an isolation region 201e, respectively.
In the logic transistor section 210 where an n-channel logic transistor is formed, a channel doped region 212 for adjusting threshold voltage is formed in a p-type well region 211. A gate electrode 214 is formed over the channel doped region 212 with a gate insulating film 213 between. The gate electrode 214 is made up of three layers, that is to say, of a polycrystalline silicon layer 214a, a silicide layer 214b, and a cap film 214c. A low concentration source region 215 and low concentration drain region 216 which are doped with n-type impurities are formed in the Si substrate 200 on both sides of the gate electrode 214.
The structure of the logic transistor section 220 where a p-channel logic transistor is formed is the same as that of the logic transistor section 210. A channel doped region 222 is formed in an n-type well region 221. A gate electrode 224 made up of a polycrystalline silicon layer 224a, a silicide layer 224b, and a cap film 224c is formed over the channel doped region 222 with a gate insulating film 223 between. A low concentration source region 225 and low concentration drain region 226 which are doped with p-type impurities are formed in the Si substrate 200 on both sides of the gate electrode 224.
In the high-breakdown-voltage transistor section 230 where an n-channel high-breakdown-voltage transistor is formed, on the other hand, a gate electrode 234 made up of a polycrystalline silicon layer 234a, a silicide layer 234b, and a cap film 234c is formed over a channel doped region 232 formed in the Si substrate 200 with a gate insulating film 233 between. The gate insulating film 233 is thicker than the gate insulating films 213 and 223 formed in the logic transistor sections 210 and 220 respectively. A low concentration source region 235 and low concentration drain region 236 which are doped with n-type impurities are formed in the Si substrate 200 on both sides of the gate electrode 234. Channel stop regions 237 and 238 doped with p-type impurities are formed near the isolation regions 201c and 201d respectively.
The structure of the high-breakdown-voltage transistor section 240 where a p-channel high-breakdown-voltage transistor is formed is the same as that of the high-breakdown-voltage transistor section 230. A channel doped region 242 is formed in an n-type well region 241. A gate electrode 244 made up of a polycrystalline silicon layer 244a, a silicide layer 244b, and a cap film 244c is formed over the channel doped region 242 with a gate insulating film 243 between. The gate insulating film 243 is thicker than the gate insulating films 213 and 223. A low concentration source region 245 and low concentration drain region 246 which are doped with p-type impurities are formed in the Si substrate 200 on both sides of the gate electrode 244. Channel stop regions 247 and 248 doped with p-type impurities are formed near the isolation regions 201d and 201e respectively.
As shown in FIG. 32, for example, the following way is used for forming sidewalls in the logic transistor sections 210 and 220. An insulating film (sidewall insulating film) 202 made of, for example, silicon oxide (SiO2) is formed on the entire surface of the above structure, the high-breakdown-voltage transistor sections 230 and 240 are covered with a resist film 203, and etching is performed. As a result, the sidewall insulating film 202 remains on the sides of the gate electrodes 214 and 224 and sidewalls are formed. The sidewalls formed in the logic transistor sections 210 and 220, together with the gate electrodes 214 and 224, are then used as masks when ion implantation is performed for forming high concentration source regions in the low concentration source regions 215 and 225 and forming high concentration drain regions in the low concentration drain regions 216 and 226.
However, if the above way is used for forming the sidewalls in the logic transistor sections 210 and 220, the shape of the sidewalls depends on the area of the resist film 203 which covers the high-breakdown-voltage transistor sections 230 and 240. To be concrete, there are many cases where if the area of the resist film 203 which covers the high-breakdown-voltage transistor sections 230 and 240 is large, the sidewalls formed in the logic transistor sections 210 and 220 spread wide. At present, it is known that if the method of forming the resist film 203 which covers the high-breakdown-voltage transistor sections 230 and 240 at the time of forming the sidewalls in the logic transistor sections 210 and 220 is adopted and the area of the high-breakdown-voltage transistor sections 230 and 240 exceeds a certain value with respect to the area of a chip, there is a strong possibility that a drop in current occurs in logic transistors finally formed due to a change in the shape of the sidewalls.
However, this problem can be avoided by forming the sidewall insulating film 202 on an entire surface and by etching the entire surface without forming the resist film 203 over the high-breakdown-voltage transistor sections 230 and 240.
FIG. 33 is a schematic sectional view showing an important part of another example of a sidewall formation process. FIG. 33 is a schematic sectional view showing a state obtained by etching the entire surface without forming the resist film 203 shown in FIG. 32. Components in FIG. 33 that are the same as those shown in FIG. 32 are marked with the same symbols and detailed descriptions of them will be omitted.
As shown in FIG. 33, it is possible to form sidewalls 217, 227, 237, and 247 in logic transistor sections 210 and 220 and high-breakdown-voltage transistor sections 230 and 240, respectively, by etching a sidewall insulating film without forming a resist film. In this case, an Si substrate 200 (low concentration source regions 215 and 225 and low concentration drain regions 216 and 226) gets exposed in the logic transistor sections 210 and 220 except under gate electrodes 214 and 224 and the sidewalls 217 and 227. However, thick gate insulating films 233 and 243 are originally formed in the high-breakdown-voltage transistor sections 230 and 240 respectively. Accordingly, the gate insulating films 233 and 243 remain on the Si substrate 200.
With this method, a resist is not used for forming the sidewalls 217 and 227 in the logic transistor sections 210 and 220 respectively. As a result, it is possible to form the sidewalls 217 and 227 each having a proper shape without taking the above influence of the resist film 203 into consideration. This prevents a deterioration in the characteristics of logic transistors.
However, if the sidewalls 217, 227, 237, and 247 are formed in this way, a problem arises in a later process for forming high concentration source and drain regions or salicide.
FIG. 34 is a schematic sectional view showing an important part of an example of a high impurity concentration region formation process. Components in FIG. 34 that are the same as those shown in FIG. 32 or 33 are marked with the same symbols and detailed descriptions of them will be omitted.
As stated above, if a sidewall insulating film is etched without forming a resist film, gate insulating films 233 and 243 remain on an Si substrate 200 (low concentration source regions 235 and 245 and low concentration drain regions 236 and 246) in high-breakdown-voltage transistor sections 230 and 240. Usually opening regions 204a, 204b, 204c, and 204d are then formed in the gate insulating film 233 on the low concentration source region 235 in the high-breakdown-voltage transistor section 230, in the gate insulating film 243 on the low concentration source region 245 in the high-breakdown-voltage transistor section 240, in the gate insulating film 233 on the low concentration drain region 236 in the high-breakdown-voltage transistor section 230, and in the gate insulating film 243 on the low concentration drain region 246 in the high-breakdown-voltage transistor section 240, respectively. Ions are implanted from the opening regions 204a, 204b, 204c, and 204d. 
In this case, it is preferable from the viewpoint of securing breakdown voltage that edges of high concentration drain regions formed in the drain regions in the high-breakdown-voltage transistor sections 230 and 240 should be separate from an edge on the gate electrode 234 or 244 side or on the isolation region 201d or 201e side of the low concentration drain region 236 or 246. Accordingly, the opening regions 204c and 204d on the drain regions in the high-breakdown-voltage transistor sections 230 and 240 should be formed so that the gate insulating films 233 and 243 will be left inside by predetermined distance from the edges on the gate electrode 234 and 244 sides and on the isolation region 201d and 201e sides of the low concentration drain regions 236 and 246. By leaving the gate insulating films 233 and 243 on the drain regions in this way, silicide is formed only in the opening regions 204c and 204d and the other regions function as a mask (silicide block) for blocking the formation of silicide in a silicide process performed after the ion implantation for forming high concentration source and drain regions.
As shown in FIG. 34, after the opening regions 204a, 204b, 204c, and 204d are formed, a p-channel logic transistor section 220 and the high-breakdown-voltage transistor section 240 are covered with a resist film 205 and the gate electrode 234 in the n-channel high-breakdown-voltage transistor section 230 is covered with the resist film 205. In this case, edges of the resist film 205 should be on the gate electrode 234 and the isolation region 201d sides from edges of the opening region 204c in the n-channel high-breakdown-voltage transistor section 230 with, for example, a positional deviation at the time of forming the resist film 205 taken into consideration so that the resist film 205 will not be formed in the opening region 204c on the drain region. In this state, ion implantation is performed to form the high concentration source and drain regions in an n-channel logic transistor sections 210 and the high-breakdown-voltage transistor section 230. Ion implantation for forming the high concentration source and drain regions in the p-channel logic transistor section 220 and the high-breakdown-voltage transistor section 240 is performed in the same way.
However, when the above ion implantation is performed, the number of impurities which pierce through the gate insulating films 233 and 243, that is to say, the number of impurities which are introduced into the Si substrate 200 may depend on the remaining thickness of the gate insulating films 233 and 243 or the area of exposed portions not covered with the resist film 205 in the opening regions 204c and 204d on the drain regions in the high-breakdown-voltage transistor sections 230 and 240. As a result, positions where the high concentration source and drain regions are formed may deviate from target places to the gate electrode 234 or 244 side or the isolation region 201d or 201e side.
In other words, if ion implantation regions for forming the high concentration source and drain regions are defined by a resist film, the ion implantation regions, that is to say, the positions where the high concentration source and drain regions are formed may depend on positions where the resist film is formed. This leads to variation or a drop in the breakdown voltage of high-breakdown-voltage transistors finally formed.
The semiconductor device in which two or more kinds of transistors (logic transistors and high-breakdown-voltage transistors, in the above example) are formed on one substrate has been described as an example. However, the above problem of variation or a drop in breakdown voltage may arise not only in semiconductor devices in which two or more kinds of transistors are formed on one substrate but also in semiconductor devices which are fabricated by forming silicide blocks on low impurity concentration regions with, for example, an insulating film and by forming high impurity concentration regions beneath opening regions by ion implantation.